1. Field of the Invention
The present invention relates generally to techniques which are used during the fabrication of semiconductor devices. More specifically, the invention relates to a technique which uses multiple mappings of critical dimensions of selected features formed on a wafer during the process of forming integrated circuits, to enable a new fabrication/manufacturing process to be calibrated/qualified in an efficient manner and to enable the production of an a microprocessor chip wherein the speed of the processor is optimized.
2. Description of the Related Art
The speed of a processor is dependent on the degree of accuracy with which the individual features of its integrated circuit (IC) are manufactured. For example, if a line has a curve or bend in it and the width of the line varies, e.g. narrows, then the amount of resistance of the line will vary and the resulting speed with which data is transferred from one point to another will be affected/impaired. In addition, heat will be generated at the narrower, higher resistance locations. With the development of localized heating, the amount of resistance tends to be increased. This process can, of course, in the worse case scenario, escalate until such time as a hot spot causes the line to fail and the circuit associated therewith is highly impaired or rendered inoperative.
Accordingly, the process of manufacturing the microprocessor needs to be examined in order to ensure that all of the features which impact the speed and efficiency are being formed optimally and free of defects of the nature alluded to above.
The term process or method should be understood throughout the following disclosure to mean at least the combination of a number of different process or method steps including resist coating, exposure via a reticle/photolithographic operation or election beam scanning, etch/implantation mask formation, etching or implantation, etc. This term should also be taken to include the use of hardware which affect the processes or methods being carried out. For example, in order to assure the correct processing is carried out, it is necessary to ensure that the operation of a stepper and associated robotics and transport mechanisms, for example, are appropriately calibrated, the etch mixtures/recipes are tuned to the required levels to avoid under or over etching, undercutting and the like.
Calibration or qualifying of the stepper is necessary before production can begin. It is also necessary to calibrate the operation of the wafer track and associated robotics in order to determine that the wafer is being moved between and disposed in the stepper and processing chambers (e.g. etching chambers) in an optimally correct manner, and thus assure that the wafer is reproducibly set on the table of the stepper in a correctly oriented and located position, each and every time.
Further, during the fabrication of an integrated circuit (IC) it is necessary to impress images on resist coating and to etch, deposit, implant or the like, a number of times before the devices on the wafer are completed and the wafer is ready for dicing. It is, therefore, necessary to ensure that the hardware used to move the wafer(s) back and forth, manipulate and to photolithograph, is operating in a manner such that each and every wafer undergoes the same manipulations/operations during each and every stage of production. For example, accurate reproducible location of the wafer in the stepper is necessary. U.S. Pat. No. 5,392,361 issued on Feb. 21, 1998 in the name of Imaizumi et al., discloses the use of a mark on the wafer and a mark position detecting method and apparatus which uses fuzzy logic to improve alignment accuracy.
For further examples of the type of arrangements which are associated with the tool set, reference can be had to U.S. Pat. No. 4,641,071 issued in Feb. 1987 in the name of Tazawa et al, and U.S. Pat. No. 4,719357 issued in Jan. 1998 in the name of Ayata et al.
It is also necessary to ensure that all of the other processes which are conducted during the IC fabrication are also working in xe2x80x9cconcertxe2x80x9d with the hardware and the computer/numerical controls which are associated therewith. Feedback arrangements which monitor the temperature of the surface of tile wafer during plasma etching, for example, should it be used during the fabrication, is preferably checked to see if the parameter is being accurately detected and reported.
With respect to the etching process which inevitably form part of the manufacturing process, reference may be had to U.S. Pat. No. 3,909,325 issued on Sep. 30, 1975 to Church et al. which discloses an example of wet etching that uses a combination of potassium hydroxide, ethylene glycol and water. This reference is hereby incorporated herein by reference. For an example of plasma etching, reference may be had to U.S Pat. No. 4,115,184 which was issued on Sep, 19 1978 in the name of Poulsen. The content of this document is also incorporated herein by reference.
However, no matter what measures are taken, in the final analysis, the only way of determining if all of the necessary adjustments have in fact been made in all optimal manner is to make a test run and to examine the end product (viz., conduct empirical testing). However, this technique tends to leave it to chance as to which adjustment or setting needs to be fine tuned to bring this highly complex arrangement into truly optimal operational status. That is to say, the settling and arrangeent of the reticle which is set in the optics of the stepper must be carefully examined in order to determine if adjustments to this vital piece of apparatus is necessary to correct some less than desirable outcome of the IC production.
Accordingly, the present invention provides a type of feedback of approach. For example, an adjustment to the stepper operation, the robotics which move the wafers from the wafer track to the stepper table, the position to which the wafer track moves the wafers prior transfer, in combination with a possible change in the reticle or even an resist or etching recipe, may, even though it would appear contrary to what might be conventionally considered to be correct and/or appropriate, enable the end result to be improved.
Nevertheless, without some form of sophisticated analysis which can be carried out in a reliable and reproducible manner, the above types of adjustment and changes in technique amount to nothing more than guess work. Accordingly, there remains a need for a reliable technique via which microprocessor speed performance can be optimized through the identification of the problem which need to be addressed in order to achieve the required speed performance optimization.
The present invention provides a technique wherein a type of feedback control, based on accumulated critical dimension (CD) mapping data of a suitably large number of different features which are produced in an integrated circuit (IC) arrangement, is implemented in a manner that enables the optimization of microprocessor speed performance.
More specifically, the underlying technique is based on a sequence of mappings which are carried out at each of a select number of production stages/steps, and wherein CD data is accumulated during each of the mappings is examined, compared and used to determine what adjustments should be made at various stages of the manufacture to ensure that the closest possible adherence to the design requirements and, therefore, the speed performance of the microprocessor, is achieved.
In other words, the present invention enables the use of an effective to feedback control data base. For example, if the mapping of results of the etching are examined and it is found that a line width or corner is too great or too small, or the configurations of given features are not as good as is required to assure the best performance of the device (e.g., features necessary to optimize the speed performance of a microprocessor), then it is possible to determine what adjustments can/should be made to the various pieces of apparatus and/or processes which are involved in the manufacturing process so as to influence the processes at each of the stages which are involved in the process, and to instigate changes/adjustments which will enable improvements to be made and for optimized microprocessor speed performance to be realized.
In particular, this technique, in accordance with the present invention, enables the a manufacturing process be to checked/modified so as to achieve the best possible results and thus optimize speed performance of the microprocessor. Once the operation of the stepper and associated apparatus, such as a wafer track, for example, is modified/adjusted and its performance is assured, and the etching and the like type of operations which are carried out, are determined to be appropriately tuned, the amount of mapping which is subsequently used can possibly be reduced to a level which is necessary to determine that the process is running properly and that the reticle or etch recipe (for example) are optimally tuned.
More specifically, a first aspect of the invention resides in a method of optimizing microprocessor speed performance, the method comprising the steps of: mapping the critical dimensions of a predetermined plurality of microprocessor features at each of a plurality of selected exposure fields of at least one of a predetermined number of production stages or steps of a wafer on which a plurality of microprocessor circuits are fabricated; comparing the data collected at each of the mappings; and determining, from the comparison, what changes are required in a set-up of a predetermined piece of apparatus or process which is used in at least one of a plurality of production stages, needs to be adjusted in order to bring at least one critical dimension of at least one of the predetermined features into agreement with at least one of a predetermined set of design critical dimensions and thus optimize microprocessor speed performance.
In the above method the predetermined features comprise ring oscillators, turning forks, test transistors, and wafer electrical testing-purpose (WET) transistors.
A second aspect of the present invention resides in a method of optimizing microprocessor speed performance, the method comprising the steps of: exposing a predetermined number of exposure fields on the wafer using one of a photolithographic technique or an electron beam technique; developing and mapping critical dimension of all features that impact integrated circuit speed performance of a microprocessor, including ring oscillators, turning forks, test transistors, and WET transistors, which are located in the exposure field, and which are contained in a selected group of the predetermined number of exposure fields, at least two different stages of production; comparing the mapped critical dimension with a set of corresponding prerequisite critical dimension values; and adjusting an operation at least at one of the two different stages of production in order to bring the critical dimension which are derived using the mapping into accordance with a difference between the mapped critical dimension and the prerequisite critical dimension values to optimize microprocessor speed performance.
Another aspect of the present invention resides in a method of optimizing microprocessor speed performance, wherein the production of the microprocessor integrated circuitry includes the use of a stepper, a wafer track, and robotic apparatus for selectively moving a wafer between at least the stepper and a reaction chamber and for reproducibly locating the wafer in each of same, the method comprising the steps of: mapping predetermined features of a reticle which is included in the stepper, to determine a first set of critical dimension data; mounting the reticle in a stepper and operating the stepper to move the substrate into a predetermined series of positions with respect to the reticle; impressing an image produced by the reticle onto a layer of photo resist formed on the wafer at each of the predetermined series of positions to form a corresponding plurality of exposure fields; removing the portion of the photo resist effected by the image impression to develop a photo resist mask pattern; mapping the predetermined features as they are formed in the photo resist mask pattern for each of selected exposure fields selected from among the plurality of exposure fields, to determine a second predetermined set of critical dimension data for the pattern; etching the wafer through the photo resist mask pattern; removing at least one portion of the photo resist mask pattern to reveal an etched pattern formed in the wafer; mapping the predetermined features in the etched pattern corresponding to each of the selected exposure fields and recording a third set of critical dimension data; repeating the steps of impressing, removing, mapping, etching, removing and mapping, in at least one subsequent fabrication stage; a comparing the first, and at least one of the second and third sets of critical dimension data with each other and/or a predetermined set of standard critical dimension data values; and determining an adjustment to at least one step of the process which is required to reduce a difference between the third set of critical dimension data and the predetermined set of critical dimension data and to optimize microprocessor speed performance.
In the above method the step of mapping comprises mapping a predetermined plurality of exposure fields which are clustered at a center portion of the wafer. More specifically, the predetermined plurality of exposure fields is five, and the predetermined features comprise ring oscillators, turning forks, test transistors, and WET transistors.